Mr. Anvesh Katipelly
Member of Technical Staff at PayPal, Austin, Texas, United States
Anvesh Katipelly is a Senior Software Engineer, AI Product Leader, and Enterprise Platform Architect with over 11 years of experience designing and leading web, platform, and API architectures that power large-scale, customer-facing systems in the financial technology domain. His work focuses on building scalable, high-performance solutions that deliver seamless user experiences while enabling rapid experimentation, reliability, and long-term platform growth.
Throughout his career, Anvesh has specialized in architecting systems that operate at scale, supporting millions of users across web and API surfaces. He is recognized for driving technical excellence, cross-functional collaboration, and engineering best practices, enabling teams to accelerate delivery while maintaining quality, security, and compliance.
Mr. Sumeer Basha Peta
Technology Leader | Architect MarTech|AEM|AEP|AJO|E-Commerce|Healthcare
A self-driven, detail-oriented technology leader with over 14+ years of experience in strategy, architecture, people management, and the development of large-scale distributed applications, focusing on delivering value to business operations.
Highly adaptable, collaborative, and skilled team player with excellent communication and leadership skills. Proven expertise in strategy, roadmap, and implementation of digital transformation, cloud migration, and platforms of strategic importance.
Expert in CMS—AEM and Contentful.
Adobe Multi-Solution architect with solid experience around Adobe Experience Platform (AEP)/CDP, Adobe Target, Adobe Journey Optimizer (AJO), and Web SDK
React, Angular, Web Components, Java
AWS/GCP Multi-Cloud Architect
Dr.Javed G S
Analog IP Design Manager, Intel Foundry & Chair, IEEE CNAG Bangalore
A creative problem solver for innovative solutions and passionate analog design manager. 30+ IEEE Journals / Conference Papers. 16 years of Analog Design expertise.
At Intel:
– Analog IP Design Manager – Intel Advanced Design (8GHz PLLs, Anaview upto 4GHz, DFT ADCs, LDOs – First Time Silicon Proven)
– Analog Lead for Parallel Memory Interface/ Die-to-Die Interconnnect at Intel, from 2020 (3 IEEE Papers)
– HBM3, DDR5 – Memory Interface Design, Loopback Testing, Documentation
– SoC Customer support for GPIO designs
– Rewarded for being Customer Centric, driving Fearless innovation and delivering solutions with Quality focused.
IEEE Eta Kappa Nu HKN Inductee – Class of 2016 – Mu Xi Chapter
Expertise:
Analog and Mixed Signal IC Design,
High Speed SerDes Transceivers (1.25 – 20 Gbps), Duty Cycle Correctors, IP Power Delivery
High Speed Low Power Interfaces (PCIe G4, MIPI MPHY G4, USB 3.2, Ethernet 10GE) – Datapath and Clockpath
PLL (2.5GHz Ring, 5 GHz Ring and 10GHz LC),
Sigma Delta ADC for Lab on Chip (13.5b @ 10KHz)
Frequency Doublers for 20GHz
LDOs, LVRs (5mA to 230mA)
Post Silicon Testing, characterization and Debug
Multiple Full Chip Tape-out experience